MScEng research project, University of Stellenbosch, South Africa, 2005-2006. Funded by SunSpace.
Soft-core processors implemented on SRAM-based FPGAs offer low-cost, flexible processing on-board satellites. However, radiation-induced single-event upsets can disrupt the expected functionality, especially when using designs where a lot of state is maintained.
In this research project I investigated mechanisms to improve the resilience of designs to single-event upsets. A Xilinx Picoblaze processor on a Spartan-III FPGA served as reference, several different designs with varying levels of error mitigation were implemented.
To measure the contribution made by different mechanisms, I constructed a low cost (USD200) fault injection platform. This tool corrupts the configuration bitstream, to simulate flipped bits in the configuration memory.
The fault-injection measurements were in turn verified through irradiation with high energy protons. When the fault injection and proton irradiation results are combined, the different parts of the single-event cross-sections can be estimated.
The final result is a set of tools and processes to transform a functional design into a resilient implementation, with quantifiable error mitigation overhead.